Methods of forming 3D devices with dielectric isolation and a strained channel region

US9397200B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventor

• Yi Qi · Niskayuna, US

Key dates

• Filing date: Sep 28, 2015
• Grant date: Jul 19, 2016
• Expiry date: Sep 28, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

One illustrative method involves forming a FinFET device or a nanowire device by forming a sacrificial gate structure above a substantially vertically oriented structure comprised of first and second semiconductor materials, forming epi semiconductor material in the source/drain regions, removing the sacrificial gate structure so as to define a replacement gate cavity and to expose the first and second semiconductor materials within the gate cavity, performing an etching process through the replacement gate cavity to selectively remove the exposed first sacrificial semiconductor material relative to the exposed second semiconductor material so as to define a gap under the second semiconductor material within the gate cavity, filling the gap with an insulating material, and forming a replacement gate structure in the gate cavity.