Method and system of collective failure diagnosis for multiple electronic circuits
US9400311B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31703
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.