Diagnosis and debug with truncated simulation
US9404972B2 · kind B2 · utility
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13References
38Claims
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Key dates
| Filing date | Oct 5, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Oct 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.