Delayed execution of program code on multiple processors
US9405315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Aug 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.