Merged source/drain and gate contacts in SRAM bitcell
US9406616B2 · kind B2 · utility
5Cited by
0References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Dec 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.