Method and structure for vertical tunneling field effect transistor and planar devices

US9406669B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Yi-Ren Chen · Miaoli City, TW
• Chi-Wen Liu · Baoshan, TW
• Chao-Hsiung Wang · Baoshan, TW
• Ming Zhu · Singapore, SG

Key dates

• Filing date: Mar 11, 2013
• Grant date: Aug 2, 2016
• Expiry date: Mar 11, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856

Abstract

The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET.