Logic finFET high-K/conductive gate embedded multiple time programmable flash memory
US9406689B2 · kind B2 · utility
18Cited by
7References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 2, 2013 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Oct 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.