FinFET conformal junction and high EPI surface dopant concentration method and device
US9406752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Apr 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.