MRAM integration techniques for technology scaling
US9406875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Mar 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.