Methodology for pattern density optimization
US9411924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2013 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Oct 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.