Layout design for manufacturing a memory cell
US9412742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern. The second interconnection layout pattern overlaps the isolation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.