Magnetoresistive device design and process integration with surrounding circuitry
US9412786B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Oct 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.