FinFET with channel backside passivation layer device and method

US9412871B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Gerben Doornbos · Kessel-Lo, BE
• Mark van Dal · Linden, BE
• Georgios Vellianitis · Heverlee, BE
• Blandine Duriez · Brussels, BE
• Krishna Kumar Bhuwalka · Suwon-si, KR
• Richard Kenneth Oxland · Brussels, BE
• Martin Christopher Holland · Leuven, BE
• Yee-Chaung See · Austin, US
• Matthias Passlack · Overijse, BE

Key dates

• Filing date: Mar 8, 2013
• Grant date: Aug 9, 2016
• Expiry date: Jun 19, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/751

Abstract

A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.