Memory controller and method for interleaving DRAM and MRAM accesses
US9418001B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Aug 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.