Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory
US9418009B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Aug 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.