Optimizing placement of circuit resources using a globally accessible placement memory
US9418188B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2016 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Jan 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.