Memory device with reduced neighbor memory cell disturbance
US9418735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Apr 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.