Patent · US Active

Stacked die integrated circuit

US9418924B2 · kind B2 · utility

4Cited by

0References

19Claims

0Family size

Assignee

Invensas LLC · US

Inventors

Charles G. Woychik · San Jose, US
Cyprian Emeka Uzoh · San Jose, US
Ron Zhang · Sunnyvale, US
Daniel Buckminster · Amherst, US
Guilian Gao · San Jose, US

Key dates

Filing date	Mar 20, 2014
Grant date	Aug 16, 2016
Priority date	—
Expiry date	Mar 20, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.