Method and apparatus for store durability and ordering in a persistent memory architecture

US9423959B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Subramanya R. Dulloor · Hillsboro, US
• Sanjay Kumar · Hillsboro, US
• Rajesh M. Sankaran · Portland, US
• Gilbert Neiger · Portland, US
• Richard Uhlig · Hillsboro, US
• Robert S. Chappell · Portland, US
• Joseph Nuzman · Aberdeen, US
• Kai Cheng · Portland, US
• Sailesh Kottapalli · San Jose, US
• Yen-Cheng Liu · Portland, US
• Mohan J. Kumar · Beaverton, US
• Raj K. Ramanujan · Federal Way, US
• Glenn J. Hinton · Portland, US

Key dates

• Filing date: Jun 29, 2013
• Grant date: Aug 23, 2016
• Expiry date: Nov 13, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/1668
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.