Method and apparatus for screening memory cells for disturb failures
US9424911B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Dec 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.