Resistive memory apparatus and memory cell thereof
US9424914B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.