Mask pattern for hole patterning and method for fabricating semiconductor device using the same
US9425072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Oct 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.