Methods of facilitating fabricating transistors
US9425100B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2015 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Apr 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and transistors for circuit structures are provided. The methods include, for instance: defining a channel region in a substrate, the channel region having at least one channel region sidewall adjoining an isolation material; recessing the isolation material to expose an upper portion of the at least one channel region sidewall; and providing a gate structure over a gate interface area with the channel region. The gate interface area includes at least the upper portion of the at least one channel region sidewall and an upper surface of the channel region so that a threshold voltage of the gate structure may be reduced. The methods may also include etching an elongate notch in the upper portion of the at least one channel region sidewall to increase a size of the gate interface area and further reduce the threshold voltage of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.