Multiple threshold voltage FinFETs
US9425196B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2015 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Dec 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a plurality of fins having different threshold voltages from a single semiconductor layer without channel doping. The method may include; forming a first semiconductor having a uniform thickness in an unmerged region, a first merged region, and a second merged region; recessing the first semiconductor in the first and second merged regions, the first semiconductor has a different thickness in each of the unmerged region, the first merged region, and the second merged region; forming a second semiconductor on the first semiconductor in the first and second merged regions; merging the first and second semiconductors to form a first merged semiconductor in the first merged region and a second merged semiconductor in the second merged region; and forming fins in unmerged region, the first merged region, and the second merged region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.