Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology

US9425206B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Wei-Cheng Wu · Hengshan, TW
• Ya-Chen Kao · Taoyuan, TW
• Shih-Chang Liu · Guanmiao, TW
• Fang-Lan Chu · Taichung, TW

Key dates

• Filing date: Dec 23, 2014
• Grant date: Aug 23, 2016
• Expiry date: Dec 23, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.