Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US9425277B2 · kind B2 · utility
16Cited by
59References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2012 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Nov 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical device in which an interface layer comprising arsenic is disposed between and in contact with a conductor and a semiconductor. In some cases, the interface layer may be a monolayer of arsenic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.