Integrated circuits with fets having nanowires and methods of manufacturing the same

US9425318B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Jan Hoentschel · Dresden, DE
• Stefan Flachowsky · Dresden, DE
• Gerd Zschaetzsch · Dresden, DE

Key dates

• Filing date: Feb 27, 2015
• Grant date: Aug 23, 2016
• Expiry date: Feb 27, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.