Damascene process of RRAM top electrodes
US9425391B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2015 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Mar 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.