Reliability test screen optimization
US9429619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2012 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jan 15, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.