Patent · US Active

Solution for full speed, parallel DUT testing

US9429623B2 · kind B2 · utility

7Cited by

2References

19Claims

0Family size

Assignee

ADVANTEST CORPORATION · JP

Inventors

W Scott Villareal Filler · Santa Clara, US
Ahmed S. Tantawy · San Jose, US
Erik Volkerink · San Jose, US

Key dates

Filing date	May 27, 2011
Grant date	Aug 30, 2016
Priority date	—
Expiry date	Aug 5, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/56
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.