Interaction of transactional storage accesses with other atomic semantics
US9430166B2 · kind B2 · utility
6Cited by
5References
26Claims
0Family size
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Key dates
| Filing date | Oct 12, 2012 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | May 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.