Wire bond through-via structure and method
US9431275B2 · kind B2 · utility
1Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2011 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Nov 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.