STI recess method to embed NVM memory in HKMG replacement gate technology
US9431413B2 · kind B2 · utility
3Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Nov 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.