Enhanced method of introducing a stress in a transistor channel by means of sacrificial sources/drain regions and gate replacement
US9431538B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 24, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Nov 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.