ECC bypass using low latency CE correction with retry select signal
US9436548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2013 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Feb 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.