Processor interrupt interface with interrupt partitioning and virtualization enhancements
US9436626B2 · kind B2 · utility
2Cited by
35References
20Claims
0Family size
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Key dates
| Filing date | Aug 9, 2012 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Sep 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.