Uniform, damage free nitride etch
US9437449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Nov 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J37/32357
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.