Chip-embedded packages with backside die connection
US9437516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2014 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | May 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces. The metal clip is embedded in the insulating material above the die and bonded to the second surface of the die. Part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die. Other embodiments of semiconductor packages are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.