Substrate for semiconductor package and process for manufacturing
US9437532B2 · kind B2 · utility
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69References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0367
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.