NAND flash memory having an enhanced buffer read capability and method of operation thereof
US9442798B2 · kind B2 · utility
3Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Dec 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.