Ring networks for intra- and inter-memory I/O including 3D-stacked memories
US9443561B1 · kind B1 · utility
19Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | May 21, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | May 21, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are described for a communications interconnect scheme for 3D stacked memory devices. A ring network design is used for networks of memory chips organized as individual devices with multiple dies or wafers. The design comprises a three-tier ring network where each ring serves a different set of memory blocks. One ring or set of rings interconnects memory within a die (inter-bank), a second ring or set of rings interconnects memory across die in a stack (inter-die), and the third ring or set of rings interconnects memory across stacks or chip packages (inter-stack).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.