Resistive memory apparatus and writing method thereof
US9443587B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Jul 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.