Method for programming a non-volatile memory cell comprising a shared select transistor gate
US9443598B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | May 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.