Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical polishing (CMP) process
US9443763B2 · kind B2 · utility
2Cited by
18References
27Claims
0Family size
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Key dates
| Filing date | Sep 12, 2013 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Aug 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.