Method to reduce metal fuse thickness without extra mask
US9443801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Mar 30, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.