FinFET with constrained source-drain epitaxial region
US9443854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Oct 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a plurality of fins on a substrate, conformally depositing a nitride liner above and in direct contact with the plurality of fins and the substrate, removing a top portion of the nitride liner above the plurality of fins to expose a top surface of the plurality of fins, forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed, forming spacers on opposite sidewalls of the nitride liner on the second portion of the plurality of fins, removing the second portion of the plurality of fins to form a trench between opposing sidewalls of the nitride liner, and forming an epitaxial layer in the trench, the lateral growth of the epitaxial layer is constrained by the nitride liner to form constrained source-drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.