System and method for visualization of NoC performance based on simulation output
US9444702B1 · kind B1 · utility
51Cited by
76References
17Claims
0Family size
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Key dates
| Filing date | Feb 6, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Feb 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0888
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure are directed to methods, systems, and non-transitory computer readable mediums for selective visualization and performance characterization of one or more transactions/messages or subsets of transaction/message of a System-on-Chip (SoC) and/or Network-on-Chip (NoC), with respect to latency, throughput, packet size, data size, hop-to-hop latency breakdown, load of one or more channels, power states of one or more elements of the NoC system, transaction data, among other like performance attributes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.