Wafer-level packaging of integrated devices, and manufacturing method thereof
US9446943B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 27, 2014 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Jun 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer-level packaging, comprising: a first semiconductor body integrating a MEMS structure; a second semiconductor body, including a surface electrical-contact region and an ASIC coupled to the MEMS structure and to said electrical-contact region; a first coating layer, made of resin, which englobes and protects the first body, the second body, and the electrical-contact region; at least one first conductive through via, which extends through the first coating layer in an area corresponding, and electrically coupled, to the first electrical-contact region; an electrical-contact pad, which extends over the first coating layer, electrically coupled to the first conductive through via; a third semiconductor body, integrating an electronic circuit, glued on the first coating layer; a second coating layer, made of resin, which englobes and protects the third body; at least one second conductive through via, which extends completely through the second coating layer in an area corresponding, and electrically coupled, to the electrical-contact pad; and a further electrical-contact pad electrically coupled to the second conductive through via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.