Storage device with robust error correction scheme
US9448880B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | May 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of enhancing error correction in a data storage system, including receiving a data storage system having one or more rows each row having: a set of data bits including a word of data, a first set of error correction bits and a second set of error correction bits or a flag bit or both; each bit can be in a first state or a second state; wherein initially all the bits are in the first state; writing data in a word in the data storage system by changing bits from the first state to the second state; creating an error correction code for the word and writing it to the first set of error correction bits; when needing to update the word using the second set of error correction bits and/or the flag bit to reduce the need to rewrite the word because of the error correction code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.