Block and zone erase algorithm for memory
US9449698B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for erasing a memory device. In one aspect, different zones of a block can be separately erased and subject to a verify test. Erase parameters can be optimized for each zone, so that endurance is improved. If one zone is found to be too slow to erase, it can be marked as being bad while other zones remain available for use. In another aspect, the zone-based erase occurs after a block based erased when a criterion is met, such as the block-based erase being too slow or failing to complete within an allowable number of program loops. The zone-based erase can occur after the block-based erase in the same erase operation, or in a subsequent, new erase operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.